1. Field of the Invention
The present invention relates to a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.
2. Description of the Related Art
A CMOS (complementary metal-oxide semiconductor) type solid-state image pickup device is known as a solid-state image pickup device. This CMOS type solid-state image pickup device is composed of a plurality of pixels arranged in a predetermined pattern in which one pixel is comprised of a photodiode and a plurality of transistors, that is, so-called MOS (metal-oxide semiconductor) transistors. The photodiode is a photoelectric converting device for generating and accumulating signal electric charges corresponding to a received amount of incident light.
FIG. 1 of the accompanying drawings is a schematic cross-sectional view showing an example of a related-art CMOS type solid-state image pickup device that is applied to an image sensor. FIG. 1 shows, in particular, a main portion of the pixel. As shown in FIG. 1, in this CMOS type solid-state image pickup device 51, a pixel separation region 65 for separating each pixel is formed on a first conductivity type, for example, p type silicon semiconductor substrate 52. A photodiode 53 and a plurality of MOS transistors, that is, four MOS transistors of an electric charge readout transistor 54, a reset transistor 55, an amplifying transistor 56 and a vertical selection transistor (not shown) are formed on each separated region and thereby a unit pixel 60 is constructed. Then, a large number of pixels 60 are arrayed in a two-dimensional matrix fashion (that is, in an XY matrix fashion).
The photodiode 53 is composed of a second conductivity type, that is, an n type semiconductor region 61 [n+ regions 61a, 61b] formed from the surface of the p type semiconductor substrate with a predetermined depth by ion implantation and a p type semiconductor region (p+ region) 62 with a high impurity concentration formed on the surface of the n type semiconductor region 61.
Each of MOS transistors 54, 55 and 56 is constructed as follows. On the surface of the p type semiconductor substrate 52, there are formed n type semiconductor regions with a high impurity concentration, that is, n+ source-drain regions 57, 58 and 59 by ion implantation so as to adjoin the photodiode 53.
The electric charge readout transistor 54 is composed of an n+ source-drain region 57, an n+ region 61a with a high impurity concentration on the surface side of the photodiode 53 and a gate electrode 72 formed on the substrate 72 between the two regions 57 and 61a through a gate insulating film 71.
The reset transistor 55 is composed of n+ source-drain regions 57 and 58 and a gate electrode 73 formed on the substrate 52 between the two regions 57 and 58 through the gate insulating film 71. The n+ source-drain region 57 is what might be called a floating diffusion (FD) region.
The amplifying transistor 56 is composed of n type source-drain regions 58 and 59 and a gate electrode 74 formed on the two regions 58 and 59 through the gate insulating film 71.
Although not shown, in a like manner, the vertical selection transistor is comprised of a pair of source-drain regions and a gate electrode formed on the substrate 52 between the two regions through a gate insulating film.
Circuit interconnections of the respective MOS transistors are similar to those which will be described later on and therefore need not be described. The n type source-drain region 58 for connecting the reset transistor 55 and the amplifying transistor 56 of each pixel is connected to a power supply interconnection 76 through a connector conductor 75. Further, a multilayer interconnection 77 including the power supply interconnection 76 is formed on the substrate 52 through an interlayer insulator 78.
This CMOS type solid-state image pickup device 51 introduces light from the surface side of the semiconductor substrate 52 into the photeodiode 53, it photoelectically converts incident light by the photodiode 53 and then it accumulates signal electric charges corresponding to the received amount of incident light.
A cited patent reference 1 has proposed a solid-state image pickup device of an MOS type image sensor in which a photodiode, an electric charge readout transistor, a reset transistor, an amplifying transistor and a vertical transfer transistor comprising the above-mentioned unit pixel are formed on the same plane of the same substrate (see cited patent reference 1).
[Cited patent reference 1]: Official Gazette of Japanese Laid-open Patent Application No. 11-122532
Although the above-mentioned CMOS type solid-state image pickup device 51 is microminiaturized in order to integrate a large number of pixels 60 with a high integration degree, since a plurality of transistors such as the photodiode 53 and the electric charge readout transistor is disposed on the same plane of, in particular, each pixel region, each pixel requires the area on the plane and it is unavoidable that the area of one pixel is increased. For this reason, it becomes difficult to microminiaturize the pixel size. When the pixel size is microminiaturized, the area of the photodiode 53 is decreased and problems arise, in which the saturated electric charge amount (Qs) is lowered and in which sensitivity is lowered.